1. Field of the Invention
The present invention relates to a write buffer FIFO architecture, and more particularly to a write buffer FIFO architecture with random access snooping capability.
2. Description of the Related Art
Write buffers are used within systems to provide temporary storage for write data. A write buffer is conceptually a FIFO (First-In-First-Out) device where data is posted at a front end of the FIFO and is retrieved from a back end of the FIFO. Data "marches" through a FIFO and emerges or is read from the back end of the FIFO in the strict ordering in which the data is written into the front end of the FIFO. A FIFO implemented as "circular queue" with dual ported random access memory (RAM), generally includes a read pointer which points to the "next" location or rank in the FIFO where data is to be read and a write pointer which points to the "next" rank in the FIFO where data is to be written. The write pointer is used by the front end logic of the FIFO to address a rank where data is to be written into the FIFO, and the read pointer is used by the back end logic of the FIFO to address a rank where data is to be retrieved from the FIFO. A device which may be termed a "producer" sends write data to the FIFO location corresponding to the write pointer, and a device which may be termed a "consumer" retrieves write data from the FIFO location corresponding to the read pointer. In most systems, a processor or bus master serves as the "producer" and a memory device, peripheral device, memory bus, or peripheral bus serves as the "consumer."
The general FIFO function of posting, buffering, and retrieving write data provided by conventional write buffer FIFOs can be inefficient when a write cycle is used to post write data to an address "related" to an address for which write data was previously posted. An address is "related" to an address for which write data was previously posted if an address is the same or contiguous with the address for which write data was previously posted such that data for both addresses is capable of storage in a single rank. A rank is a unit or space of a write buffer FIFO used for data or address storage. A write buffer FIFO typically includes a plurality of ranks for data storage and a plurality of ranks for address storage. For a write cycle of a conventional write buffer FIFO, a new rank is allocated and new write data is posted to the new rank. The new write data, however, may be provided for an address "related" to an address for which write data is already stored in an existing rank. This event occurs when data was previously posted for an address "related" to the address provided for the new write data. Multiple write cycles thus may be used to post write data associated with "related" addresses to multiple ranks. Since a FIFO has a limited number of ranks, each rank constitutes valuable FIFO space.
The conventional write buffer FIFO approach of allowing write data for "related" addresses to be spread across multiple ranks requires multiple read cycles to retrieve the write data for "related" addresses. For each read cycle, write data is retrieved from a single rank. Multiple read cycles therefore may be required to fully retrieve write data even for "related" addresses. If the multiple ranks containing write data for "related" addresses are interleaved with ranks containing write data for other addresses, it has been necessary to retrieve write data for "related" addresses as well as the data for other addresses from the interleaved ranks due to the strict ordering in which write data is retrieved from a conventional write buffer FIFO. Speed is an important concern in retrieving FIFO data. For a conventional write buffer FIFO, the need to execute multiple read cycles to retrieve write data for "related" addresses thus extends the time for retrieving FIFO data for "related" addresses.
Further, to maintain data coherency, it has been necessary to flush (or empty) the data stored in a conventional write buffer to the consumer (e.g., a memory device) before servicing a read request of a consumer address that also is "related" to an address held in the buffer address store. Flushing of the write buffer ensures that the most recent data is written to the consumer before the consumer responds to the read request. Thus, read requests which involve an address related to an address in the buffer are delayed.